With continuous improvements of the semiconductor technologies, a system is developing in a multi-core direction. To meet a requirement of the system for high concurrency and a low latency of on-chip communication, a network-on-chip (NoC) gradually displaces a bus to become a mainstream interconnection scheme inside a chip. However, as a feature size of an integrated circuit technique continues to shrink, electrical interconnection and transmission faces great performance deteriorating in terms of latency and power consumption. Compared with a traditional electrical interconnection manner, optical interconnection has advantages, such as a low latency, a low loss, and anti-interference, and therefore, as a way of effectively resolving a potential problem of electrical interconnection, optical interconnection has attracted much attention in recent years. Optical interconnection is being introduced to the NoC, and becomes an on-chip structure of a high potentiality—an optical network-on-chip (ONoC).
Although with continuous improvements of the semiconductor integrated circuit processing technologies, a breakthrough has been made in manufacturing most optical devices, an optical caching technology compatible with a complementary metal-oxide-semiconductor (CMOS) technique is still not yet mature, which makes it difficult to temporarily store optical information in a transmission process. Therefore, electrical network configuration and optical network transmission are mostly used in a current ONoC.
Currently, there is an ONoC and a communication method that are based on wavelength allocation, where the ONoC uses a mesh topology structure, and uses a routing algorithm similar to X-Y. The ONoC includes multiple nodes, a structure of the ONoC is shown in FIG. 1A, and each circle in FIG. 1A indicates one node. A structure of each node is shown in FIG. 1B, and each circle in FIG. 1B includes one microring resonator (MRR).
A basic working principle of the NoC shown in FIG. 1A is as follows. In an optical information transmission process, each node completes X-Y turning using four MRRs shown in an origin in FIG. 1B, and turning wavelengths of each row and each column are different, which avoids interference, implements simultaneous transmission of optical information of multiple nodes in a same waveguide, and improves waveguide bandwidth utilization. When the optical information is being sent, two groups of MRRs (MRRs in the left direction of an x-axis and MRRs in the right direction of the x-axis) below modulate the information as optical information of a wavelength required for turning, and transmits the optical information to a waveguide in the direction of X. When the optical information arrives at an intermediate node that is in a same Y-axis as a destination node, four MRRs at an origin of the intermediate node turn the optical information to the direction of Y. When the optical information arrives at the destination node, vertical MRRs that are of the destination node and of corresponding wavelengths transmit the optical information to an optical-to-electrical converter for completing optical-to-electrical conversion, and information obtained after optical-to-electrical conversion is sent to a processing unit, where IP in FIG. 1B is a processor or a memory.
The foregoing ONoC uses a routing algorithm similar to X-Y, and only one path exists between a source node and a destination node. Adaptive adjustment cannot be performed on a transmission path according to a network status, and network congestion is likely to occur when load is imbalanced.